Alice in the wonderland of Formal Verification
A
verification engineer is a detective for Silicon – a Formal verification
engineer is a verification engineer on steroids.
If you Google, “How much time is spent on verification in RTL Development?” You will find yourself uttering one of the many adjectives of great surprise! Design Verification takes almost 80% of the overall time spent on chip development and verification engineers lose hair, sleep, peace, patience and a pinch of weekends on tight deadlines to deliver the quality of verification.
Any attempts to cut short the efforts or expedite the process is a giant leap in correct direction. Formal verification is rising and shining like a superhero in the ever-growing complex field of verification. It is the ring of power in the current market and surely gives a boost to your career in FrontEnd Verification. Being skilled in Formal Verification ensures you a ticket to be highly employable in semiconductors at-least for the next decade.
Formal Verification is an advanced skill and comes with a list of pre-requisites to extract the most out of this role.
The following are the chief pre-requisites to develop an acumen of a formal verification
engineer:
1. Formal Verification as a verification technique: Why is it required ? How is it different from dynamic verification? What exactly is Formal Verification? Different methods for performing Formal Verification?
2. System Verilog Assertions
3. Coverage using Formal Verification methods
4. Knowledge of standard Formal Tools and Formal verification Apps: FPV, FRV, CC, FXV, etc. FPV being the most important of them all.
5. (ADAVNCED and MOST IMPORTANT) You should be thorough with the Abstraction techniques and how to make formal model faster. This is THE MOST important and most sought-after skill in any Formal Verification Engineer. Please don’t rush into this and focus on the basics first before diving deep into this topic.
I highly recommend going through my handwritten notes for starters to develop some understanding about the topic. Following is the list of books you need to refer to become HIGHLYYYY proficient in Formal Verification.
Necessary and Sufficient List of Resources:
1. Formal Verification: An Essential Toolkit for Modern VLSI Design
-Starting chapters gives you a complete overview of the need and advantages of Formal verification.
-After developing some understanding of what Formal is, you should focus on the FPV as a tool. To make the most out of FPV you should have some grip over SVA so you can learn SVA in parallel to this. Refer to Ashok B Mehta’s book on SVA. It covers all the topics and is extremely beginner friendly.
2. Ashok B. Mehta: SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications
- I highly recommend this book to anyone who is breaking into the formal verification. It covers all the required details about the SVA and the author has also shared insights from his experience in verification domain.
- I recommend solving the in chapter Assertion questions on your own before actually looking into the solution.
3. Ramdas Course on SVA : Free on Udemy
- This is an introductory course and touches almost all the topics but not in much depth. It is a free resource and you can watch this as an introduction to the topics and get some sense check about the field. If you prefer video lectures over the books, this will serve it’s purpose but I still recommend going through the above 2 books at least to develop a good grasp over the subject.
Course Link: CLICK_HERE
(ADVANCED RESOURCES) : Refer them for the abstraction techniques and how to optimize formal models
4. Formal Verification For Digital Circuit Design by Douglas Perry
5. A Roadmap for Formal Property Verification by Pallab Das Gupta
NOTE: To download any of the above book you can use ZLibray using Tor Browser. Please comment on this blog if you need help in downloading the Ebooks.
LINK TO ZLibrary - CLICK_HERE (Works without TOR Browser as well)
1. Formal Verification as a verification technique: Why is it required ? How is it different from dynamic verification? What exactly is Formal Verification? Different methods for performing Formal Verification?
2. System Verilog Assertions
3. Coverage using Formal Verification methods
4. Knowledge of standard Formal Tools and Formal verification Apps: FPV, FRV, CC, FXV, etc. FPV being the most important of them all.
5. (ADAVNCED and MOST IMPORTANT) You should be thorough with the Abstraction techniques and how to make formal model faster. This is THE MOST important and most sought-after skill in any Formal Verification Engineer. Please don’t rush into this and focus on the basics first before diving deep into this topic.
I highly recommend going through my handwritten notes for starters to develop some understanding about the topic. Following is the list of books you need to refer to become HIGHLYYYY proficient in Formal Verification.
Necessary and Sufficient List of Resources:
1. Formal Verification: An Essential Toolkit for Modern VLSI Design
-Starting chapters gives you a complete overview of the need and advantages of Formal verification.
-After developing some understanding of what Formal is, you should focus on the FPV as a tool. To make the most out of FPV you should have some grip over SVA so you can learn SVA in parallel to this. Refer to Ashok B Mehta’s book on SVA. It covers all the topics and is extremely beginner friendly.
2. Ashok B. Mehta: SystemVerilog Assertions and Functional Coverage: A guide to language, methodology and applications
- I highly recommend this book to anyone who is breaking into the formal verification. It covers all the required details about the SVA and the author has also shared insights from his experience in verification domain.
- I recommend solving the in chapter Assertion questions on your own before actually looking into the solution.
3. Ramdas Course on SVA : Free on Udemy
- This is an introductory course and touches almost all the topics but not in much depth. It is a free resource and you can watch this as an introduction to the topics and get some sense check about the field. If you prefer video lectures over the books, this will serve it’s purpose but I still recommend going through the above 2 books at least to develop a good grasp over the subject.
Course Link: CLICK_HERE
(ADVANCED RESOURCES) : Refer them for the abstraction techniques and how to optimize formal models
4. Formal Verification For Digital Circuit Design by Douglas Perry
5. A Roadmap for Formal Property Verification by Pallab Das Gupta
I have covered the complete strategy to crack VLSI jobs along with thorough notes in the this blog. I will be regularly sharing best resources for preparation as well as upskilling. Please share this post in your network – hopefully this could help someone achieve their dream.
BLOG: PLACEMENT PREP RESOURCES
Follow me for more insightful content! 💯
LinkedIn
Telegram
NOTE: To download any of the above book you can use ZLibray using Tor Browser. Please comment on this blog if you need help in downloading the Ebooks.
LINK TO ZLibrary - CLICK_HERE (Works without TOR Browser as well)
Comments
Post a Comment